1. Field of the Invention
This invention relates generally to the design of integrated circuits (ICs), and more particularly, to the performance analysis of ICs.
2. Description of the Related Art
In the manufacture of modern integrated circuits, the size of circuit elements has been reduced to the nanometer scale. Each new technological advancement entails tighter manufacturing process control requirements. For example, in the optical lithography process, circuit element sizes are significantly smaller than the wavelength of light used in optical lithography, resulting in a “sub-wavelength lithography” regime. This requires advanced photomasks that embody one or more reticle enhancement techniques, such as optical proximity correction of mask aperture shapes, the insertion of sub-resolution assist circuit elements, phase-shifting, and so forth.
However, not even leading-edge photomask making and other related technologies can compensate for unavoidable manufacturing process variations. These variations include, notably, variations in focus and dose amount. Variations in focus (i.e., “defocus”) are errors in the positioning of the ideal image plane relative to the wafer. The dose amount is the amount of radiant energy that reaches the wafer surface. As a result of such process variations, the integrated circuit element shapes printed on the wafer often fail to match the element shapes drawn by the designer with an acceptable level of accuracy. The element shapes drawn by the designer are simulated with respect to photomask and/or process steps before they are actually printed on the wafer. This simulation, which we refer to generically as “lithography simulation”, generates “lithography-simulated shapes”, or, simply, “printed shapes” that serve as predictions of the actual printed shapes on the wafer. Correct verification of the IC design should typically require that the element shapes, as printed on the wafer, i.e., the lithography-simulated shapes and not the shapes drawn by the designer, are analyzed to determine the performance parameters of the IC. These performance parameters include the actual static power, dynamic power, total power, signal delay, signal integrity, circuit timing, reliability, manufacturing yield, and other performance characteristics.
The lithography-simulated shapes can be irregular, and known circuit analysis tools are unable to handle the complexity of these shapes efficiently. For example, circuit simulators, such as HSPICE™ from Synopsys, typically require transistors to be composed entirely of rectangles. Parasitic extractors, such as Raphael™ from Synopsys, QuickCap™ from Magma, Star-RCXT™ from Synopsys, and Fire & Ice™ from Cadence, are typically also limited to a small set of primitive shapes that are defined by axis-parallel edges. Since the underlying computer data structures and algorithms are dramatically simplified and have faster runtimes when straight-line edges and/or axis-parallel edges are assumed, existing circuit analysis tools have been limited to these types of primitive shapes. These circuit analysis tools cannot inherently analyze complex lithography-simulated shapes. Further, the runtime of parasitic extractors, critical-area analysis tools, and other analysis tools generally increases monotonically with the total number of vertices or edges in the set of input shapes.
These limitations effectively prevent analysis and optimization of the IC design, based on the lithography-simulated shapes. This discrepancy, with respect to the circuit elements on the polysilicon layer of the IC, can result in inaccurate transistor dimensions being used in performance analysis. Inaccurate wire widths may be used with respect to circuit elements on the interconnect layers. With respect to circuit elements on contacts/vias layers, the outcome can be an inaccurate coverage area, resulting in incorrect evaluations of reliability and resistance. Overall, these limitations can result in inaccuracy in analyses and optimizations of the IC design, including, but not limited to, those addressing system performance and power, and loss of performance and parametric yield in manufactured ICs.
Therefore, there is a need for a method and a system and that can analyze an IC for various performance characteristics, based on the lithography-simulated IC circuit elements rather than on the drawn layout of those circuit elements. The method and system should be capable of being used in the design cycle, to iterate the design of the IC, and make use of existing and known circuit analysis tools.